AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents I/O Bank 2K, Lanes 0,1,2 (Addr/Cmd)

The Arria 10 External Memory Interface (EMIF) for HPS IP core uses the Hard Memory Controller (HMC) located in I/O Bank 2K, which results in lanes 0, 1 and 2 being used for the address and command signals. The address and command signals are at fixed locations within these I/O lanes.

GUIDELINE: Unused pins in I/O Lanes 0, 1 and 2 of I/O Bank 2K are available as FPGA GPIO.

Pins not utilized by the Arria 10 EMIF for HPS IP core for address and command in I/O Bank 2K, lanes 0, 1 and 2 are available to the FPGA fabric as general purpose I/O. FPGA GPIO signals assigned to unused pin locations in these lanes support I/O standards compatible with I/O Bank 2K’s VCCIO and VREF supply levels, which are dictated by the external SDRAM’s signaling standard.