AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents ECC for External SDRAM Interface

ECC on the HPS external SDRAM interface is implemented in the SDRAM Adapter. The SDRAM Adapter’s ECC controller performs SECDED on both the address and data to ensure valid data accesses at the intended locations in memory.

Note: For details on the SDRAM Adapter's ECC controller, refer to the "System Interconnect" section, Functional Description of the SDRAM Adapter section, and the "ecc_hmc_ocp_slv_block" Address Map under Register Definitions section of the Intel® Arria® 10 Hard Processor System Technical Reference Manual.

GUIDELINE: Initialize All SDRAM Regions.

You must initialize all regions of the external SDRAM that any part of the SoC system may access through the SDRAM Adapter before enabling ECC, including program code and data regions and other regions of memory accessed by FPGA masters and L2 cache line fetches. Consider extended regions for initialization when the L2 cache is enabled, because cache line fetches could extend beyond the program code and data footprint, resulting in likely bit errors from uninitialized RAM locations. You can define and configure memory regions for ECC scrubbing with the bsp-editor utility in the Intel® SoC FPGA EDS tool chain.

GUIDELINE: Consider SDRAM Adapter ECC Write Behavior.

For partial writes (less than the SDRAM memory interface width), the adapter implements a read-modify-write sequence to maintain the ECC bits for the entire interface word width. Consider how narrow accesses might affect bandwidth and latency for your application while writing firmware and application software as well as accesses from other masters in the system.

For more information about using the EMIF with 16-bit data and ECC enabled, refer to Intel® Arria® 10 SX Device Errata and Design Recommendations.