AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

4.5.7. UART Interface Design Guidelines

GUIDELINE: Properly connect flow control signals when routing the UART signals through the FPGA fabric.

When routing UART signals through the FPGA, the flow control signals are available. If flow control is not being used, connect the signals in the FPGA as shown in the following table:
Table 10.  UART Interface Design
Signal Direction Connection
CTS input low
DSR input high
DCD input high
RI input high
DTR output No-Connection
RTS output No-Connection
OUT1_N output No-Connection
OUT2_N output No-Connection