AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents HPS-Initiated Configuration

When the device is powered and the HPS begins executing the software in the boot ROM, all the device I/O default to an input tri-state mode of operation. The boot ROM configures the dedicated boot I/O based on the sampled BSEL pins. At this time during the boot process the only I/O that are configured are the HPS Dedicated I/O which are connected to the HPS flash device and all other I/O remain in the default input tri-state mode of operation. The second stage bootloader configures the remaining dedicated HPS boot I/O as well as the FPGA and HPS Shared I/O by either configuring the entire FPGA or just the HPS Shared I/O and HPS DDR I/O by configuring the early I/O release bitstream.

HPS Early I/O Release

The HPS-initiated configuration flows supports a feature called early I/O release. The early I/O release feature allows you to minimize the HPS boot time by configuring the device I/O independent of configuring the majority of the FPGA fabric.

This feature reduces the HPS boot time because the majority of the FPGA configuration file is used to configure FPGA fabric with a small portion being used to configure the I/O. The I/O portion of the configuration file is used to configure the HPS shared I/O, HPS SDRAM I/O and remaining FPGA I/O. The HPS dedicated I/O are not affected by the FPGA configuration bitstream.

By configuring the I/O independent of the FPGA fabric, the HPS SDRAM controller becomes functional so that the HPS boot loader can populate the SDRAM with the next stage boot contents. After the I/O has been configured, the rest of the FPGA fabric can be configured immediately or by an application after booting completes.

GUIDELINE: With early I/O release, use a fixed power supply for startup.

If you are using the early I/O release configuration flow, you cannot initially use SmartVID to power your device. Instead, you can use a fixed power supply until after the FPGA is configured. When the FPGA is configured, you can then enable SmartVID.

GUIDELINE: Since the dedicated HPS I/O are the only pins not affected by configuring the device I/O, it is important to place any interfaces that must remain functional through a configuration cycle in the dedicated I/O bank. If access to HPS peripherals and HPS SDRAM is desired during boot, then the device must be configured using HPS Early I/O release mode.

For example, if your system requires a UART to remain operational while the FPGA is being configured, you should use dedicated I/O for the UART. If the HPS boot source is going to be external flash then the flash must be connected to the dedicated HPS I/O so that they remain functional while the rest of the I/O is being configured. For other use cases refer to the FPGA Reconfiguration section of this document.

HPS Initiated FPGA Core Configuration

If FPGA configuration fails (due to a bit error for example), the HPS shared and SDRAM I/Os are placed in an input tristate mode. If the HPS initiates FPGA configuration after an early I/O release, and configuration fails, any HPS access to a shared I/O peripheral or HPS SDRAM fails because of the tri-stated I/Os. HPS dedicated I/Os are not affected.

This behavior has no impact on full FPGA configuration using a Raw Binary File (.rbf) that contains both the FPGA core and configuration. In this case, the HPS can access HPS shared I/O and HPS SDRAM only after the device has been successfully configured.

GUIDELINE: Provide a configuration failure avoidance or recovery mechanism that does not rely on access to HPS shared I/Os or HPS SDRAM.

If software executes from SDRAM, you can avoid this issue by performing a configuration bitstream checksum in software before initiating configuration. For example, the .rbf can have a cyclic redundancy check (CRC), which software can validate before programming the file contents into the FPGA core.

GUIDELINE: Enable ECC to avoid correctable bitstream corruption issues.

If software executes entirely from on-chip RAM, and a configuration failure occurs, software can recover by reprogramming the peripheral configuration .rbf to reactivate the HPS shared and SDRAM I/Os.

After the I/Os have been reconfigured, software can reconfigure the FPGA fabric, either with the same image or with a fallback image (to prevent the same failure from recurring).

It is recommended that before configuring the rest of the FPGA fabric that software perform an integrity check of the bitstream first. The purpose of this integrity check is to avoid configuration issues due to bitstream corruption. If the bitstream is corrupt, then configuration of the FPGA fabric fails and all of the device I/O except the HPS Dedicated I/O is reverted to an input tri-state mode of operation.