AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Document Table of Contents

4.5.1. HPS EMAC PHY Interfaces

When configuring an HPS component for EMAC peripherals within Platform Designer, you must select from one of the following supported PHY interfaces for each EMAC instance:
  • Reduced Media Independent Interface (RMII) using Shared I/O
  • Reduced Gigabit Media Independent Interface (RGMII) using Shared I/O
  • Media Independent Interface (MII) interface to FPGA fabric
  • Gigabit Media Independent Interface (GMII) interface to FPGA fabric

Any combination of supported PHY interface types can be configured across multiple HPS EMAC instances.

GUIDELINE: For RMII and RGMII using Shared I/O, develop an early I/O floor-planning template design to ensure that there are enough Shared I/O to accommodate the chosen PHY interfaces in addition to other HPS peripherals planned for Shared I/O usage.

Note: Refer to the HPS Component section for guidelines on configuring the HPS component.

It is possible to adapt the MII/GMII PHY interfaces exposed to the FPGA fabric by the HPS component to other PHY interface standards such as RMII, SGMII, SMII and TBI through the use of soft adaptation logic in the FPGA and features in the general-purpose FPGA I/O and transceiver FPGA I/O.

GUIDELINE: When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the skew control feature, and device driver availability.

Note: Refer to the device drivers available for your OS of choice or the Linux device driver provided with the Intel® Arria® 10 SoC development kit. (Golden System Reference Design)

You can connect the Intel® Arria® 10 HPS embedded Ethernet MAC (EMAC) PHY interfaces directly to industry standard Gigabit Ethernet PHYs using the RGMII interface and 10/100 Ethernet PHYs using the RMII interface at any supported I/O voltage using the Shared I/O pins in the HPS 3V I/O bank. These voltages typically include 1.8V, 2.5V and 3.0V. If you use Shared I/O pins for the PHY interface, then no FPGA routing resources are used and timing is fixed, simplifying timing on the interface. This document describes the design guidelines for RGMII and RMII, the most typical interfaces.

You can also connect PHYs to the HPS EMACs through the FPGA fabric using the GMII and MII bus interfaces for Gigabit and 10/100 Mbps access respectively.

GUIDELINE: A GMII-to-SGMII adapter is available to automatically adapt to transceiver-based SGMII optical modules.