AN 763: Intel® Arria® 10 SoC Device Design Guidelines

ID 683192
Date 5/17/2022
Public
Document Table of Contents

2.1.4. FPGA-to-SDRAM Ports

GUIDELINE: Use the FPGA-to-SDRAM ports for non-cacheable access to the HPS SDRAM from masters in the FPGA.

The FPGA-to-SDRAM ports allow masters implemented in the FPGA fabric to directly access HPS SDRAM without the transactions flowing through the L3 Main Interconnect. These interfaces connect only to the HPS SDRAM subsystem so use them in your design if the FPGA needs high-throughput, low-latency access to the HPS SDRAM. The exception to this recommendation is if the FPGA requires cache coherent access to SDRAM. The FPGA-to-SDRAM interfaces cannot access the MPU ACP slave so if you require a master implemented in the FPGA to access cache coherent data, ensure that it is connected to the FPGA-to-HPS bridge instead.

There are three FPGA-to-SDRAM ports with ports FPGA-to-SDRAM0 and FPGA-to-SDRAM2 supporting 32, 64, and 128-bit datapaths and FPGA-to-SDRAM1 supporting 32 and 64-bit datapaths. Four combinations of port configurations are available with the maximum aggregate bandwidth being available when FPGA-to-SDRAM0 and FPGA-to-SDRAM2 are setup for 128-bit datapaths. Each FPGA-to-SDRAM port is serviced independently including the ports connect to the L3 Main Interconnect and the MPU. The four possible FPGA-to-SDRAM port combinations are listed in the following table:

Table 5.  Available FPGA-to-SDRAM Port Combinations

Port Configuration

FPGA-to-SDRAM0

FPGA-to-SDRAM1

FPGA-to-SDRAM2

1

32 bits

32 bits

32 bits

2

64 bits

64 bits

64 bits

3

128 bits

Unavailable

128 bits

4

128 bits

32 bits

64 bits

GUIDELINE: Ensure that data accessed by the FPGA through the FPGA-to-SDRAM ports is flushed from the level 1 (L1) and level 2 (L2) caches before accessing data via the FPGA-to-SDRAM ports.

This ensures the latest copy of data is resident in SDRAM before the FPGA attempts to access the data.