1. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs
2. Guidelines for Interconnecting the Intel® Arria® 10 HPS and FPGA
3. Design Guidelines for HPS Portion of Arria 10 SoC FPGAs
4. Board Design Guidelines for Arria 10 SoC FPGAs
5. Embedded Software Design Guidelines for Arria 10 SoC FPGAs
1.1. SoC FPGA Designer's Checklist
1.2. Overview of HPS Design Guidelines for SoC FPGA design
1.3. Overview of Board Design Guidelines for SoC FPGA Design
1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design
1.5. Overview of Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
2.1.1. HPS-to-FPGA Bridge
2.1.2. Lightweight HPS-to-FPGA Bridge
2.1.3. FPGA-to-HPS Bridge
GUIDELINE: Use the FPGA-to-HPS bridge for cacheable accesses to the HPS from masters in the FPGA.
GUIDELINE: Use the FPGA-to-HPS bridge to access cache-coherent memory, peripherals, or on-chip RAM in the HPS from masters in the FPGA.
2.1.4. FPGA-to-SDRAM Ports
2.1.5. Interface Bandwidths
3.1. Start your SoC FPGA design here
3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory
3.3. HPS Clocking and Reset Design Considerations
3.4. HPS EMIF Design Considerations
3.5. DMA Considerations
3.6. Design Guidelines for HPS Portion of Intel® Arria® 10 SoC FPGAs Revision History
4.1. Power On Board Bring Up and Boot ROM/Boot Loader Debugging
4.2. FPGA Reconfiguration
4.3. HPS Power Design Considerations
4.4. Boundary Scan for HPS
4.5. Design Guidelines for HPS Interfaces
4.6. Connection Guidelines for Unused HPS Block
4.7. Board Design Guidelines for Intel® Arria® 10 SoC FPGAs Revision History
4.5.1. HPS EMAC PHY Interfaces
4.5.2. USB Interface Design Guidelines
4.5.3. QSPI Flash Interface Design Guidelines
4.5.4. SD/MMC and eMMC Card Interface Design Guidelines
4.5.5. Provide Flash Memory Reset for QSPI and SD/MMC/eMMC
4.5.6. NAND Flash Interface Design Guidelines
4.5.7. UART Interface Design Guidelines
4.5.8. I2C Interface Design Guidelines
5.1.1. Purpose
5.1.2. Assembling the components of your Software Development Platform
5.1.3. Selecting an Operating System for your application
5.1.4. Assembling your Software Development Platform for Linux
5.1.5. Assembling your Software Development Platform for a Bare-Metal Application
5.1.6. Assembling your Software Development Platform for Partner OS or RTOS
5.1.7. Choosing Boot Loader Software
5.1.8. Selecting Software Tools for Development, Debug and Trace
5.1.9. Board Bring Up Considerations
5.1.10. Boot and Configuration Design Considerations
5.1.11. Flash Device Driver Design Considerations
5.1.12. HPS ECC Design Considerations
5.1.13. Security Design Considerations
5.1.14. Embedded Software Debugging and Trace
5.1.10.1.1. Boot Source
5.1.10.1.2. Select Desired Flash Device
5.1.10.1.3. BSEL Options
5.1.10.1.4. Boot Clock
5.1.10.1.5. Determine Boot Fuses Usage
5.1.10.1.6. CSEL Options
5.1.10.1.7. Determine Flash Programming Method
5.1.10.1.8. Selecting NAND Flash Devices
5.1.10.1.9. Selecting QSPI Flash Devices
5.1.10.1.10. Reference Materials
2.1.3. FPGA-to-HPS Bridge
GUIDELINE: Use the FPGA-to-HPS bridge for cacheable accesses to the HPS from masters in the FPGA.
The FPGA-to-HPS bridge allows masters implemented in the FPGA fabric to access memory and peripherals inside the HPS. This bridge supports 32, 64, and 128-bit data paths so that you can adjust it to be as wide as the widest master implemented in the FPGA.
GUIDELINE: Use the FPGA-to-HPS bridge to access cache-coherent memory, peripherals, or on-chip RAM in the HPS from masters in the FPGA.
Although this bridge has direct connectivity to the SDRAM subsystem, the main intent of the bridge is to provide access to peripherals and on-chip memory, as well as provide cache coherency with connectivity to the MPU accelerator coherency port (ACP).
To access the HPS SDRAM directly without coherency, you should connect masters in the FPGA to the FPGA-to-SDRAM ports instead, because they provide much more bandwidth and lower-latency access.