Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Document Table of Contents

10.2. Verilog HDL Prototype11.2. Verilog HDL Prototype

To view the Verilog HDL prototype for the IP core, refer to the Verilog Design File (.v) altera_mf.v in the < Intel® Quartus® Prime installation directory>\eda\synthesis directory.

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