Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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11.5. Ports

The following tables list the input and output ports for the ALTMULT_ADD IP core.

Table 47.  ALTMULT_ADD Input Ports
Port Name Required Description
dataa[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1..0] wide.
datab[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1..0] wide.
clock[] No Clock input port [0..3] to the corresponding register. This port can be used by any register in the IP core.
aclr[] No Input port [0..3]. Asynchronous clear input to the corresponding register.
ena[] No Input port [0..3]. Clock enable for the corresponding clock[] port.
signa No Specifies the numerical representation of the dataa[] port. If the signa port is high, the multiplier treats the dataa[] port as a signed two's complement number. If the signa port is low, the multiplier treats the dataa[] port as an unsigned number.
signb No Specifies the numerical representation of the datab[] port. If the signb port is high, the multiplier treats the datab[] port as a signed two's complement number. If the signb port is low, the multiplier treats the datab[] port as an unsigned number.
Table 48.  ALTMULT_ADD Input Ports (Stratix IV Devices Only)
Port Name Required Description
Ports Available in Stratix IV devices only
output_round No Enables dynamically controlled output rounding. When OUTPUT_ROUNDING is set to VARIABLE, output_round enables the final adder stage of rounding.
output_saturate No Enables dynamically controlled output saturation. When OUTPUT_SATURATION is set to VARIABLE, output_saturate enables the final adder stage of saturation.
chainout_round No Enables dynamically controlled chainout stage rounding. When CHAINOUT_ROUNDING is set to VARIABLE, chainout_round enables the chainout stage of rounding.
chainout_saturate No Enables dynamically controlled chainout stage saturation. When CHAINOUT_SATURATION is set to VARIABLE, chainout_saturate enables the chainout stage of saturation.
zero_chainout No Dynamically specifies whether the chainout value is zero.
zero_loopback No Dynamically specifies whether the loopback value is zero.
accum_sload No Dynamically specifies whether the accumulator value is zero.
chainin No Adder result input bus from the preceding stage. Input port [WIDTH_CHAININ - 1..0] wide.
rotate No Specifies dynamically controlled port rotation in shift mode.
shift_right No Specifies dynamically controlled port shift right or left in shift mode. Values are 0 and 1. A value of 0 specifies a shift to the left, a value of 1 specifies a shift to the right.
Table 49.  ALTMULT_ADD Output Ports
Port Name Required Description
result[] Yes Multiplier output port. Output port [WIDTH_RESULT - 1..0] wide.
overflow No Overflow flag. If output_saturation is enabled, overflow flag is set.
scanouta[] No Output of scan chain A. Output port [WIDTH_A - 1..0] wide. Do not use scanina[] and scaninb[] simultaneously.
scanoutb[] No Output of scan chain B. Output port [WIDTH_B - 1..0] wide. Do not use scanina[] and scaninb[] simultaneously.
Table 50.  ALTMULT_ADD Output Ports (Stratix IV Devices Only)
Port Name Required Description
chainout_sat_overflow No Overflow flag for the chainout saturation.

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