Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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9.4. Ports

The following tables list the input and output ports for the ALTMEMMULT IP core.
Table 37.  ALTMEMMULT Input Ports
Port Name Required Description
clock Yes Clock input to the multiplier.
coeff_in[] No Coefficient input port for the multiplier. The size of the input port depends on the WIDTH_C parameter value.
data_in[] Yes Data input port to the multiplier. The size of the input port depends on the WIDTH_D parameter value.
sclr No Synchronous clear input. If unused, the default value is active high.
sel[] No Fixed coefficient selection. The size of the input port depends on the WIDTH_S parameter value.
sload_coeff No Synchronous load coefficient input port. Replaces the current selected coefficient value with the value specified in the coeff_in input.
sload_data No Synchronous load data input port. Signal that specifies new multiplication operation and cancels any existing multiplication operation. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the sload_data input port is ignored.
Table 38.  ALTMEMMULT Output Ports
Port Name Required Description
result[] Yes Multiplier output port. The size of the input port depends on the WIDTH_R parameter value.
result_valid Yes Indicates when the output is the valid result of a complete multiplication. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the result_valid output port is not used.
load_done No Indicates when the new coefficient has finished loading. The load_done signal asserts when a new coefficient has finished loading. Unless the load_done signal is high, no other coefficient value can be loaded into the memory.

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