Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2. Verilog HDL Prototype

The following Verilog HDL prototype is located in the Verilog Design File (.v) lpm.v in the < Intel® Quartus® Prime installation directory>\eda\synthesis directory.

module lpm_add_sub ( result, cout, overflow,add_sub, cin, dataa, datab, clock, clken, aclr );
parameter lpm_type = "lpm_add_sub";
parameter lpm_width = 1;
parameter lpm_direction  = "UNUSED";
parameter lpm_representation = "SIGNED";
parameter lpm_pipeline = 0;
parameter lpm_hint = "UNUSED";
input  [lpm_width-1:0] dataa, datab;
input  add_sub, cin;
input  clock;
input  clken;
input  aclr;
output [lpm_width-1:0] result;
output cout, overflow;