Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

14.1. Feature

The PARALLEL_ADD IP core offers the following features:

  • Performs add or subtract operations on a number of inputs to produce a single sum result
  • Supports data width of 8–128 bits
  • Supports signed and unsigned data representation format
  • Supports pipelining with configurable output latency
  • Supports shifting data vectors
  • Supports addition or subtraction of the most-significant input operands
  • Supports optional asynchronous clear and clock enable ports

Did you find the information on this page useful?

Characters remaining:

Feedback Message