Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

8.6.2. Extra Modes Tab

Table 31.  Extra Modes Tab
Parameter IP Generated Parameter Value Default Value Description
Outputs Configuration
Register output of the adder unit gui_output_register

On

Off

Off

Select this option to enable output register of the adder module.

What is the source for clock input? gui_output_register_clock

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the clock source for output registers.

You must select Register output of the adder unit to enable this parameter.

What is the source for asynchronous clear input? gui_output_register_aclr

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

What is the source for synchronous clear input? gui_output_register_sclr

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

Adder Operation
What operation should be performed on outputs of the first pair of multipliers? gui_multiplier1_direction

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the first and second multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select more than two multipliers to enable this parameter.

Register 'addnsub1' input gui_addnsub_multiplier_register1

On

Off

Off Select this option to enable input register for addnsub1 port.

You must select VARIABLE for What operation should be performed on outputs of the first pair of multipliers to enable this parameter.

What is the source for clock input? gui_addnsub_multiplier_register1_clock

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

What is the source for asynchronous clear input? gui_addnsub_multiplier_aclr1

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

What is the source for synchronous clear input? gui_addnsub_multiplier_sclr1

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

What operation should be performed on outputs of the second pair of multipliers? gui_multiplier3_direction

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the third and fourth multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select the value 4 for What is the number of multipliers? to enable this parameter.

Register 'addnsub3' input gui_addnsub_multiplier_register3

On

Off

Off Select this option to enable input register for addnsub3 signal.

You must select VARIABLE for What operation should be performed on outputs of the second pair of multipliers to enable this parameter.

What is the source for clock input? gui_addnsub_multiplier_register3_clock

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

What is the source for asynchronous clear input? gui_addnsub_multiplier_aclr3

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

What is the source for synchronous clear input? gui_addnsub_multiplier_sclr3

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

Polarity
Enable ‘use_subadd’ gui_use_subnadd

On

Off

Off

Select this option to reverse the function of addnsub input port.

Drive addnsub to high for subtraction operation.

Drive addnsub to low for addition operation.

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