Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

14.5. Ports

The following tables list the input and output ports of the PARALLEL_ADD IP core.

Table 58.  PARALLEL_ADD Input Ports
Port Name Required Description
data[] Yes Data input to the parallel adder. Input port [SIZE - 1 DOWNTO 0, WIDTH-1 DOWNTO 0] wide.
clock No Clock input to the parallel adder. This port is required if the PIPELINE parameter has a value of greater than 0.
clken No Clock enable to the parallel adder. If omitted, the default value is 1.
aclr No Active high asynchronous clear input to the parallel adder.
Table 59.  PARALLEL_ADD Output Ports
Port Name Required Description
result[] Yes Adder output port. The size of the output port depends on the WIDTHR parameter value.

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