7.1. ALTECC Encoder Features
The ALTECC encoder IP core offers the following features:
- Performs data encoding using the Hamming Coding scheme
- Supports data width of 2–64 bits
- Supports signed and unsigned data representation format
- Support pipelining with output latency of either one or two clock cycles
- Supports optional asynchronous clear and clock enable ports
The ALTECC encoder IP core takes in and encodes the data using the Hamming Coding scheme. The Hamming Coding scheme derives the parity bits and appends them to the original data to produce the output code word. The number of parity bits appended depends on the width of the data.
The following table lists the number of parity bits appended for different ranges of data widths. The Total Bits column represents the total number of input data bits and appended parity bits.
|Data Width||Number of Parity Bits||Total Bits (Code Word)|
The parity bit derivation uses an even-parity checking. The additional 1 bit (shown in the table as +1) is appended to the parity bits as the MSB of the code word. This ensures that the code word has an even number of 1’s. For example, if the data width is 4 bits, 4 parity bits are appended to the data to become a code word with a total of 8 bits. If 7 bits from the LSB of the 8-bit code word have an odd number of 1’s, the 8th bit (MSB) of the code word is 1 making the total number of 1’s in the code word even.
The following figure shows the generated code word and the arrangement of the parity bits and data bits in an 8-bit data input.
The ALTECC encoder IP core accepts only input widths of 2 to 64 bits at one time. Input widths of 12 bits, 29 bits, and 64 bits, which are ideally suited to Intel® devices, generate outputs of 18 bits, 36 bits, and 72 bits respectively. You can control the bit-selection limitation in the parameter editor.
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