Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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7.8. Decoder Ports

The following tables list the input and output ports for the ALTECC decoder IP core.

Table 24.  ALTECC Decoder Input Ports
Port Name Required Description
data[] Yes Data input port. The size of the input port depends on the WIDTH_CODEWORD parameter value.
clock Yes Clock input port that provides the clock signal to synchronize the encoding operation. The clock port is required when the LPM_PIPELINE value is greater than 0.
clocken No Clock enable. If omitted, the default value is 1.
aclr No Asynchronous clear input. The active high aclr signal can be used at any time to asynchronously clear the registers.
Table 25.  ALTECC Decoder Output Ports
Port Name Required Description
q[] Yes Decoded data output port. The size of the output port depends on the WIDTH_DATAWORD parameter value.
err_detected Yes Flag signal to reflect the status of data received and specifies any errors found.
err_corrected Yes Flag signal to reflect the status of data received. Denotes single-bit error found and corrected. You can use the data because it has already been corrected.
err_fatal Yes Flag signal to reflect the status of data received. Denotes double-bit error found, but not corrected. You must not use the data if this signal is asserted.
syn_e No An output signal which will go high whenever a single-bit error is detected on the parity bits.

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