Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
Public
Document Table of Contents

8.6.1. General Tab

Table 30.  General Tab
Parameter IP Generated Parameter Value Default Value Description
What is the number of multipliers? number_of_multipliers

1 - 4

1 Number of multipliers to be added together. Values are 1 up to 4.
How wide should the A input buses be? width_a 1 - 256 16 Specify the width of the dataa[] port.
How wide should the B input buses be? width_b 1 - 256 16 Specify the width of the datab[] port.
How wide should the 'result' output bus be? width_result 1 - 256 32 Specify the width of the result[] port.
Create an associated clock enable for each clock gui_associated_clock_enable

On

Off

Off Select this option to create clock enable for each clock.

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