Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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12.8. Signals

Table 53.  ALTMULT_COMPLEX Input Signals
Signal Required Description
aclr No Asynchronous clear for the complex multiplier. When the aclr signal is asserted high, the function is asynchronously cleared.
sclr No Synchronous clear for the complex multiplier. When the sclr signal is asserted high, the function is asynchronously cleared.

Only available for Intel® Stratix® 10, Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

clock Yes Clock input to the ALTMULT_COMPLEX function.
dataa_imag[] Yes Imaginary input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value.
dataa_real[] Yes Real input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value.
datab_imag[] Yes Imaginary input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value.
datab_real[] Yes Real input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value.
ena No Active high clock enable for the clock signal of the complex multiplier.
complex No Optional input to enable dynamic switching between 36 × 36 normal model and 18 × 18 complex mode.

This input is only available in Stratix V devices. In the GUI, this parameter is referred as Dynamic Complex Mode.

Table 54.  ALTMULT_COMPLEX Output Signals
Signal Required Description
result_imag Yes Imaginary output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value.
result_real Yes Real output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value.

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