Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Document Table of Contents

8. Intel FPGA Multiply Adder IP Core

The Intel FPGA Multiply Adder ( Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices) or ALTERA_MULT_ADD (Arria V, Stratix V, and Cyclone V devices) IP core allows you to implement a multiplier-adder.

The following figure shows the ports for the Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP core.

Figure 9. Intel FPGA Multiply Adder or ALTERA_MULT_ADD Ports

A multiplier-adder accepts pairs of inputs, multiplies the values together and then adds to or subtracts from the products of all other pairs.

If all of the input data widths are 9-bits wide or smaller, the function uses the 9 x 9 bit input multiplier configuration in the DSP block for devices which support 9 x 9 configuration. If not, the DSP block uses 18 × 18-bit input multipliers to process data with widths between 10 bits and 18 bits. If multiple Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP cores occur in a design, the functions are distributed to as many different DSP blocks as possible so that routing to these blocks is more flexible. Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device.

The registers and extra pipeline registers for the following signals are also placed inside the DSP block:

  • Data input
  • Signed or unsigned select
  • Add or subtract select
  • Products of multipliers

In the case of the output result, the first register is placed in the DSP block. However the extra latency registers are placed in logic elements outside the block. Peripheral to the DSP block, including data inputs to the multiplier, control signal inputs, and outputs of the adder, use regular routing to communicate with the rest of the device. All connections in the function use dedicated routing inside the DSP block. This dedicated routing includes the shift register chains when you select the option to shift a multiplier's registered input data from one multiplier to an adjacent multiplier.

For more information about DSP blocks in any of the Stratix V, and Arria V device series, refer to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation page.

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