Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

14.2. Verilog HDL Prototype

The following Verilog HDL prototype is located in the Verilog Design File (.v) altera_mf.v in the < Intel® Quartus® Prime installation directory>\eda\synthesis directory.

module parallel_add (
    data,
    clock,
    aclr,
    clken,
    result);
    parameter width = 4; 
    parameter size = 2; 
    parameter widthr = 4; 
    parameter shift = 0;
    parameter msw_subtract = "NO";  // or "YES"
    parameter representation = "UNSIGNED";
    parameter pipeline = 0;
    parameter result_alignment = "LSB"; // or "MSB"
    parameter lpm_type = "parallel_add";
    input [width*size-1:0] data;
    input clock; 
    input aclr; 
    input clken; 
    output [widthr-1:0] result;
endmodule

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