Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
Public
Document Table of Contents

4.6.3. Pipelining Tab

Table 11.   Pipelining Tab
Parameter Value Default Value Description
Do you want to pipeline the function?

No

Yes

No Select Yes to enable pipeline register to the multiplier's output and specify the desired output latency in clock cycle. Enabling the pipeline register adds extra latency to the output.
Create an 'aclr' asynchronous clear port Unchecked

Select this option to enable aclr port to use asynchronous clear for the pipeline register.

Create a 'clken' clock enable clock Unchecked Specifies active high clock enable for the clock port of the pipeline register
Optimization
What type of optimization do you want?

Default

Speed

Area

Default Specify the desired optimization for the IP core.

Select Default to let Intel® Quartus® Prime software to determine the best optimization for the IP core.

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