Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

3.5. Ports

The following tables list the input and output ports for the LPM_DIVIDE IP core.

Table 5.  LPM_DIVIDE Input Ports
Port Name Required Description
numer[] Yes Numerator data input. The size of the input port depends on the LPM_WIDTHN parameter value.
denom[] Yes Denominator data input. The size of the input port depends on the LPM_WIDTHD parameter value.
clock No Clock input for pipelined usage. For LPM_PIPELINE values other than 0 (default), the clock port must be enabled.
clken No Clock enable pipelined usage. When the clken port is asserted high, the division operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear port used at any time to reset the pipeline to all '0's asynchronously to the clock input.
Table 6.  LPM_DIVIDE Output Ports
Port Name Required Description
quotient[] Yes Data output. The size of the output port depends on the LPM_WIDTHN parameter value.
remain[] Yes Data output. The size of the output port depends on the LPM_WIDTHD parameter value.

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