Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

2.3. VHDL Component Declaration

The VHDL component declaration is located in the VHDL Design File (.vhd) LPM_PACK.vhd in the < Intel® Quartus® Prime installation directory>\libraries\vhdl\lpm directory.

component LPM_COUNTER
        	generic ( LPM_WIDTH : natural; 
                  	LPM_MODULUS : natural := 0;
                  	LPM_DIRECTION : string := "UNUSED";
                  	LPM_AVALUE : string := "UNUSED";
                  	LPM_SVALUE : string := "UNUSED";
                  	LPM_PORT_UPDOWN : string := "PORT_CONNECTIVITY";
                  	LPM_PVALUE : string := "UNUSED";
                  	LPM_TYPE : string := L_COUNTER;
                  	LPM_HINT : string := "UNUSED");
			port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS => '0');
      			CLOCK : in std_logic ;
      			CLK_EN : in std_logic := '1';
      			CNT_EN : in std_logic := '1';
      			UPDOWN : in std_logic := '1';
      			SLOAD : in std_logic := '0';
      			SSET : in std_logic := '0';
      			SCLR : in std_logic := '0';
      			ALOAD : in std_logic := '0';
      			ASET : in std_logic := '0';
      			ACLR : in std_logic := '0';
      			CIN : in std_logic := '1';
      			COUT : out std_logic := '0';
      			Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
      			EQ : out std_logic_vector(15 downto 0));
		end component;

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