Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

3.6. Parameters

The following table lists the parameters for the LPM_DIVIDE Intel FPGA IP core.

Parameter Name Type Required Description
LPM_WIDTHN Integer Yes Specifies the widths of the numer[] and quotient[] ports. Values are 1 to 64.
LPM_WIDTHD Integer Yes Specifies the widths of the denom[] and remain[] ports. Values are 1 to 64.
LPM_NREPRESENTATION String No Sign representation of the numerator input. Values are SIGNED and UNSIGNED. When this parameter is set to SIGNED, the divider interprets the numer[] input as signed two's complement.
LPM_DREPRESENTATION String No Sign representation of the denominator input. Values are SIGNED and UNSIGNED. When this parameter is set to SIGNED, the divider interprets the denom[] input as signed two's complement.
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL design files (.vhd).
LPM_HINT String No When you instantiate a library of parameterized modules (LPM) function in a VHDL Design File (.vhd), you must use the LPM_HINT parameter to specify an Intel® -specific parameter. For example: LPM_HINT = "CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YES" The default value is UNUSED.
LPM_REMAINDERPOSITIVE String No Intel® -specific parameter. You must use the LPM_HINT parameter to specify the LPM_REMAINDERPOSITIVE parameter in VHDL design files. Values are TRUE or FALSE. If this parameter is set to TRUE, then the value of the remain[] port must be greater than or equal to zero. If this parameter is set to TRUE, then the value of the remain[] port is either zero, or the value is the same sign, either positive or negative, as the value of the numer port. In order to reduce area and improve speed, Intel® recommends setting this parameter to TRUE in operations where the remainder must be positive or where the remainder is unimportant.
MAXIMIZE_SPEED Integer No Intel® -specific parameter. You must use the LPM_HINT parameter to specify the MAXIMIZE_SPEED parameter in VHDL design files. Values are [0..9]. If used, the Intel® Quartus® Prime software attempts to optimize a specific instance of the LPM_DIVIDE function for speed rather than routability, and overrides the setting of the Optimization Technique logic option. If MAXIMIZE_SPEED is unused, the value of the Optimization Technique option is used instead. If the value of MAXIMIZE_SPEED is 6 or higher, the Compiler optimizes the LPM_DIVIDE IP core for higher speed by using carry chains; if the value is 5 or less, the compiler implements the design without carry chains.
LPM_PIPELINE Integer No Specifies the number of clock cycles of latency associated with the quotient[] and remain[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinational function is instantiated. If omitted, the default value is 0 (non-pipelined). You cannot specify a value for the LPM_PIPELINE parameter that is higher than LPM_WIDTHN.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. The parameter editor calculates the value for this parameter.
SKIP_BITS Integer No Allows for more efficient fractional bit division to optimize logic on the leading bits by providing the number of leading GND to the LPM_DIVIDE IP core. Specify the number of leading GND on the quotient output to this parameter.

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