Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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4.5. Signals

Table 7.  LPM_MULT Input Signals
Signal Name Required Description
dataa[] Yes Data input.

For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, the size of the input signal depends on the Dataa width parameter value.

For older and Intel® Cyclone® 10 LP devices, the size of the input signal depends on the LPM_WIDTHA parameter value.

datab[] Yes Data input.

For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, the size of the input signal depends on the Datab width parameter value.

For older and Intel® Cyclone® 10 LP devices, the size of the input signal depends on the LPM_WIDTHB parameter value.

clock No Clock input for pipelined usage.

For older and Intel® Cyclone® 10 LP devices, the clock signal must be enabled for LPM_PIPELINE values other than 0 (default).

For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, the clock signal must be enabled if Latency value is other than 1 (default).

clken No Clock enable for pipelined usage. When the clken signal is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear signal used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
sclr No Synchronous clear signal used at any time to reset the pipeline to all 0s, synchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
Table 8.  LPM_MULT Output signals
signal Name Required Description
result[] Yes Data output.

For older and Intel® Cyclone® 10 LP devices, the size of the output signal depends on the LPM_WIDTHP parameter value. If LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) or (LPM_WIDTHA + LPM_WIDTHS), only the LPM_WIDTHP MSBs are present.

For Intel® Stratix® 10, Intel® Arria® 10 and Intel® Cyclone® 10 GX, the size of the output signals depends on the Result width parameter.

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