Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

8.1.1.3. Pre-adder Input Mode

In this mode, one multiplier operand derives from the pre-adder, and the other operand derives from the datac[] input port.

This mode is expressed in the following equation.



The following shows the pre-adder input mode of a multiplier.

Figure 12. Pre-adder Input Mode


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