Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide

Document Version Intel® Quartus® Prime Version Changes
2020.10.05 20.3 Added a note to removed ALTMEMMULT support in Intel® Quartus® Prime Pro Edition software.
2020.04.30 17.1
  • Updated values for Which multiplier implementation should be used? parameter for LPM_MULT IP core in the Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices topic.
Date Version Changes
November 2017 2017.11.24
  • Rebranded ALTERA_MULT_ADD IP core name to Intel FPGA Multiply Adder for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
  • Reverted the behavior of sload_accum and accum_sload signals in Intel FPGA Multiply Adder or ALTERA_MULT_ADD Input Signals.
  • Added Intel® Stratix® 10 devices in the List of IP Cores table.
  • Removed Design Example Files section.
  • Added a note for the first multiplier chainin signal in Systolic Delay Register.
June 2017 2017.06.19
  • Rebranded as Intel.
  • Added support for Cyclone 10 GX and Cyclone 10 LP devices.
  • Removed outdated design example information.
  • Updated sload_accum and accum_sload signals behavior in the ALTERA_MULT_ADD Input Signals table.
June 2016 2016.06.10
  • Added separate parameters table for Arria 10 devices.
  • Replaced ip-generated parameter names with GUI parameter names for LPM_MULT, ALTERA_MULT_ADD and ALTMULT_COMPLEX IP cores.
  • Added synchronous clear support for input, pipeline, and output registers LPM_MULT in Arria 10 devices, ALTERA_MULT_ADD for all devices and ALTMULT_COMPLEX for Arria 10 devices.
  • Added new parameters in LPM_MULT and ALTMULT_COMPLEX IP cores (Arria 10 devices) and ALTERA_MULT_ADD (for all devices) to enable users to select synchronous clear feature.
  • Removed resource tables for all Integer Arithmetic IP cores.
November 2015 2015.11.18
  • Corrected LPM_COUNTER VHDL component declaration.
  • Added device support list to List of IP Cores table.
  • Removed Stratix V, Arria V and Cyclone V devices support for ALTMULT_ACCUM and ALTMULT_ADD IP cores.
  • Removed Cyclone II, Cyclone III, Stratix II, and Stratix III because these devices are no longer supported for all the integer arithmetic IP cores.
  • Change COEFFSEL[]_REGISTER parameter name to COEFSEL[]_REGISTER and COEFFSEL[]_ACLR parameter name to COEFSEL[]_ACLR.
  • Added description in REPRESENTATION_A and REPRESENTATION_B parameters to clarify only signed input representation is supported for Stratix V, Arria V, Cyclone V, and Arria 10 devices.
  • Added LPM_ADD_SUB and LPM_COMPARE IP cores information.
  • Added links to Introduction to Altera IP Cores, Creating Version-Independent IP and Qsys Simulation Scripts, and Project Management Best Practices.
  • Changed instances of Quartus II to Quartus Prime.
December, 2014 2014.12.19
  • Removed the LPM_ADD_SUB and LPM_COMPARE IPs because these IPs are no longer supported.
  • Added a note to clarify that when building multipliers larger than the natively supported size there may be a performance impact resulting from the cascading of the DSP blocks in LPM_MULT, ALTERA_MULT_ADD, ALTMULT_ACCUM, ALTMULT_ADD, and ALTMULT_COMPLEX IP cores.
  • Added information about the Create a ‘sync_e’ port parameter and the sync_e signal for ALTECC_DECODER IP core.
  • Removed sconst port information as the port is no longer available for LPM_COUNTER IP core.
  • Provided an example to use the LPM_HINT parameter.
August, 2014 2014.08.18
  • Updated parameterization steps for legacy and latest parameter editors.
  • Added note for IP cores that do not support Arria 10 designs.
  • Added device migration information.
June 2014 5.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
June 2013 4.0
  • Added Intel FPGA Multiply Adder IP Core section.
  • Removed the following obsoleted megafunctions: LPM_ABS, ALTACCUMULATE, ALTMULT_ACCUM, ALTMULT_ADD.
  • Updated ALTMULT_ACCUM (Multiply-Accumulate) on page 10-1 to include an obsolescence note and remove Arria V, Cyclone V, and Stratix V devices information.
  • Updated ALTMULT_ADD (Multiply-Adder) on page 11-1 to include an obsolescence note and remove Arria V, Cyclone V, and Stratix V devices information.
February 2013 3.1
  • Updated Table 52 on page 63 to include Stratix V information for accum_sload port.
  • Updated Table 54 on page 65 to include Stratix V information for PORT_SIGNA and PORT_SIGNB parameters.
February 2012 3.0
  • Added Arria V and Cyclone V device support.
  • Updated the parameter description for the following section:
    • ALTMULT_ACCUM (Multiply-Accumulate)
    • ALTMULT_ADD (Multiply-Add)
  • Added the Double Accumulator section.
July 2010 2.0
  • Updated architecture information for the following sections:
    • ALTMULT_ACCUM (Multiply-Accumulate)
    • ALTMULT_ADD (Multiply-Add)
    • ALTMULT_COMPLEX (Complex Multiplier)
  • Added specification information for all megafunctions
November 2009 1.0 Initial release.

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