Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core

The ALTMULT_ACCUM IP core allows you to implement a multiplier-adder.

Note: This IP core is not supported in Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, and Stratix V devices and will be replaced by Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP core.

The following figure shows the ports for the ALTMULT_ACCUM IP core.

Figure 22.  ALTMULT_ACCUM Ports

A multiplier-accumulator accepts a pair of inputs, multiplies the two inputs together, and feeds their result into an accumulator to be added to or subtracted from its previous registered result. This function is expressed in the following equation.

Where N is the number of cycles of data that has been entered into the accumulator.