Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
Public
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8.1.4. Double Accumulator

The double accumulator feature adds an additional register in the accumulator feedback path. The double accumulator register follows the output register, which includes the clock, clock enable, and aclr. The additional accumulator register returns result with a one-cycle delay. This feature enables you to have two accumulator channels with the same resource count.

The following figure shows the double accumulator implementation.

Figure 20. Double Accumulator


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