Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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Document Table of Contents

8.5. Signals

The following tables list the input and output signals of the Multiply Adder Intel® FPGA IP or ALTERA_MULT_ADD IP core.

Table 28.   Multiply Adder Intel® FPGA IP or ALTERA_MULT_ADD Input Signals
Signal Required Description
dataa_0[]/dataa_1[]/dataa_2[]/dataa_3[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals,the X value is propagated on the output signals.

datab_0[]/datab_1[]/datab_2[]/datab_3[] Yes Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

datac_0[] /datac_1[]/datac_2[]/datac_3[] No Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C - 1, … 0] wide

Select INPUT for Select preadder mode parameter to enable these signals.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

clock[1:0] No Clock input port to the corresponding register. This signal can be used by any register in the IP core.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

aclr[1:0] No Asynchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

sclr[1:0] No Synchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value X to these signals. When you provide X value to these signals, the X value is propagated on the output signals

ena[1:0] No Enable signal input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

signa No Specifies the numerical representation of the multiplier input A. If the signa signal is high, the multiplier treats the multiplier input A signal as a signed number. If the signa signal is low, the multiplier treats the multiplier input A signal as an unsigned number.

Select VARIABLE for What is the representation format for Multipliers A inputs parameter to enable this signal.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

signb No Specifies the numerical representation of the multiplier input B signal. If the signb signal is high, the multiplier treats the multiplier input B signal as a signed two's complement number. If the signb signal is low, the multiplier treats the multiplier input B signal as an unsigned number.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

scanina[] No Input for scan chain A. Input signal [WIDTH_A - 1, ... 0] wide. When the INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is required.
accum_sload No Dynamically specifies whether the accumulator value is constant. If the accum_sload signal is low, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

sload_accum No Dynamically specifies whether the accumulator value is constant. If the sload_accum signal is high, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

chainin[] No Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ - 1, … 0] wide.
addnsub1 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

addnsub3 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub3 signal to add the outputs from the second pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel0[] No Coefficient input signal[0:3] to the first multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel1[] No Coefficient input signal[0:3]to the second multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel2[] No Coefficient input signal[0:3]to the third multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel3[] No Coefficient input signal [0:3] to the fourth multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

Table 29.   Multiply Adder Intel® FPGA IP Output Signals
Signal Required Description
result [] Yes Multiplier output signal. Output signal [WIDTH_RESULT - 1 … 0] wide

The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.

scanouta [] No Output of scan chain A. Output signal [WIDTH_A - 1..0] wide.

Select more than 2 for numbers of multipliers and choose Scan chain input

for What is the input A of the multiplier connected to parameter to enable this signal.

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