Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA Integer Arithmetic IP Cores 2. LPM_COUNTER (Counter) IP Core 3. LPM_DIVIDE (Divider) Intel FPGA IP Core 4. LPM_MULT (Multiplier) IP Core 5. LPM_ADD_SUB (Adder/Subtractor) 6. LPM_COMPARE (Comparator) 7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 8. Intel FPGA Multiply Adder IP Core 9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core 11. ALTMULT_ADD (Multiply-Adder) IP Core 12. ALTMULT_COMPLEX (Complex Multiplier) IP Core 13. ALTSQRT (Integer Square Root) IP Core 14. PARALLEL_ADD (Parallel Adder) IP Core 15. Integer Arithmetic IP Cores User Guide Document Archives 16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
2. LPM_COUNTER (Counter) IP Core x
2.1. Features 2.2. Verilog HDL Prototype 2.3. VHDL Component Declaration 2.4. VHDL LIBRARY_USE Declaration 2.5. Ports 2.6. Parameters
3. LPM_DIVIDE (Divider) Intel FPGA IP Core x
3.1. Features 3.2. Verilog HDL Prototype 3.3. VHDL Component Declaration 3.4. VHDL LIBRARY_USE Declaration 3.5. Ports 3.6. Parameters
4. LPM_MULT (Multiplier) IP Core x
4.1. Features 4.2. Verilog HDL Prototype 4.3. VHDL Component Declaration 4.4. VHDL LIBRARY_USE Declaration 4.5. Signals 4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices 4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices
4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices x
4.6.1. General Tab 4.6.2. General 2 Tab 4.6.3. Pipelining Tab
4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices x
4.7.1. General Tab 4.7.2. General 2 Tab 4.7.3. Pipelining
5. LPM_ADD_SUB (Adder/Subtractor) x
5.1. Features 5.2. Verilog HDL Prototype 5.3. VHDL Component Declaration 5.4. VHDL LIBRARY_USE Declaration 5.5. Ports 5.6. Parameters
6. LPM_COMPARE (Comparator) x
6.1. Features 6.2. Verilog HDL Prototype 6.3. VHDL Component Declaration 6.4. VHDL LIBRARY_USE Declaration 6.5. Ports 6.6. Parameters
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core x
7.1. ALTECC Encoder Features 7.2. Verilog HDL Prototype (ALTECC_ENCODER) 7.3. Verilog HDL Prototype (ALTECC_DECODER) 7.4. VHDL Component Declaration (ALTECC_ENCODER) 7.5. VHDL Component Declaration (ALTECC_DECODER) 7.6. VHDL LIBRARY_USE Declaration 7.7. Encoder Ports 7.8. Decoder Ports 7.9. Encoder Parameters 7.10. Decoder Parameters
8. Intel FPGA Multiply Adder IP Core x
8.1. Features 8.2. Verilog HDL Prototype 8.3. VHDL Component Declaration 8.4. VHDL LIBRARY_USE Declaration 8.5. Signals 8.6. Parameters
8.1. Features x
8.1.1. Pre-adder 8.1.2. Systolic Delay Register 8.1.3. Pre-load Constant 8.1.4. Double Accumulator
8.1.1. Pre-adder x
8.1.1.1. Pre-adder Simple Mode 8.1.1.2. Pre-adder Coefficient Mode 8.1.1.3. Pre-adder Input Mode 8.1.1.4. Pre-adder Square Mode 8.1.1.5. Pre-adder Constant Mode
8.6. Parameters x
8.6.1. General Tab 8.6.2. Extra Modes Tab 8.6.3. Multipliers Tab 8.6.4. Preadder Tab 8.6.5. Accumulator Tab 8.6.6. Systolic/Chainout Tab 8.6.7. Pipelining Tab
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core x
9.1. Features 9.2. Verilog HDL Prototype 9.3. VHDL Component Declaration 9.4. Ports 9.5. Parameters
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core x
10.1. Features 10.2. Verilog HDL Prototype 10.3. VHDL Component Declaration 10.4. VHDL LIBRARY_USE Declaration 10.5. Ports 10.6. Parameters
11. ALTMULT_ADD (Multiply-Adder) IP Core x
11.1. Features 11.2. Verilog HDL Prototype 11.3. VHDL Component Declaration 11.4. VHDL LIBRARY_USE Declaration 11.5. Ports 11.6. Parameters
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core x
12.1. Complex Multiplication 12.2. Canonical Representation 12.3. Conventional Representation 12.4. Features 12.5. Verilog HDL Prototype 12.6. VHDL Component Declaration 12.7. VHDL LIBRARY_USE Declaration 12.8. Signals 12.9. Parameters
13. ALTSQRT (Integer Square Root) IP Core x
13.1. Features 13.2. Verilog HDL Prototype 13.3. VHDL Component Declaration 13.4. VHDL LIBRARY_USE Declaration 13.5. Ports 13.6. Parameters
14. PARALLEL_ADD (Parallel Adder) IP Core x
14.1. Feature 14.2. Verilog HDL Prototype 14.3. VHDL Component Declaration 14.4. VHDL LIBRARY_USE Declaration 14.5. Ports 14.6. Parameters
1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide

12.9. Parameters

The following table lists the parameters for the ALTMULT_COMPLEX IP core.
Table 55.  ALTMULT_COMPLEX Parameters
Parameter IP Generated Parameter Value Default Value Description
General
How wide should the A input buses be? WIDTH_A 1–256 18 Specifies the number of bits for A input buses.
How wide should the B input buses be? WIDTH_B 1–256 18 Specifies the number of bits for B input buses.
How wide should the ‘result’ output bus be? WIDTH_RESULT 1–256 36 Specifies the number of bits for ‘result’ output bus.
Input Representation
What is the representation format for A inputs? REPRESENTATION_A

Signed,

Unsigned

Signed Specifies the representation format for A inputs.

Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only signed input representation format.

What is the representation format for B inputs? REPRESENTATION_B

Signed,

Unsigned

Signed Specifies the representation format for B inputs. Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only signed input representation format.
Complex Multiplier Option
Dynamic Complex Mode GUI_DYNAMIC_COMPLEX — Unchecked Enable dynamic switching between 36 x 36 normal mode and 18 x 18 complex mode.

Available only in Stratix V devices.

Implementation Style
Which implementation style should be used? IMPLEMENTATION_STYLE

Automatically select a style for best trade-off for the current settings

Canonical (Minimize the number of simple multipliers)

Conventional (Minimize the use of logic cells)

Automatically select a style for best trade-off for the current settings Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only Automatically select a style for best trade-off for the current settings style. The Intel® Quartus® Prime software determines the best implementation based on the selected device family and input width.
Pipelining (Only available for Arria 10 and Cyclone 10 GX devices)
Output latency PIPELINE 0–11 4 Specifies the number of clock cycles for output latency.
Create a Clear input? CLEAR_TYPE

NONE

ACLR

SCLR

NONE Select this option to create aclr or sclr signal for the complex multiplier.
Create a Clock Enable input? GUI_USE_CLKEN — Unchecked Select this option to create ena signal for the complex multiplier clock.
Related Information
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