Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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Document Table of Contents

12.9. Parameters

The following table lists the parameters for the ALTMULT_COMPLEX IP core.
Table 55.  ALTMULT_COMPLEX Parameters
Parameter IP Generated Parameter Value Default Value Description
General
How wide should the A input buses be? WIDTH_A 1–256 18 Specifies the number of bits for A input buses.
How wide should the B input buses be? WIDTH_B 1–256 18 Specifies the number of bits for B input buses.
How wide should the ‘result’ output bus be? WIDTH_RESULT 1–256 36 Specifies the number of bits for ‘result’ output bus.
Input Representation
What is the representation format for A inputs? REPRESENTATION_A

Signed,

Unsigned

Signed Specifies the representation format for A inputs.

Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only signed input representation format.

What is the representation format for B inputs? REPRESENTATION_B

Signed,

Unsigned

Signed Specifies the representation format for B inputs. Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only signed input representation format.
Complex Multiplier Option
Dynamic Complex Mode GUI_DYNAMIC_COMPLEX Unchecked Enable dynamic switching between 36 x 36 normal mode and 18 x 18 complex mode.

Available only in Stratix V devices.

Implementation Style
Which implementation style should be used? IMPLEMENTATION_STYLE

Automatically select a style for best trade-off for the current settings

Canonical (Minimize the number of simple multipliers)

Conventional (Minimize the use of logic cells)

Automatically select a style for best trade-off for the current settings Arria V, Intel® Arria® 10, Cyclone V, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Stratix V devices support only Automatically select a style for best trade-off for the current settings style. The Intel® Quartus® Prime software determines the best implementation based on the selected device family and input width.
Pipelining (Only available for Arria 10 and Cyclone 10 GX devices)
Output latency PIPELINE 0–11 4 Specifies the number of clock cycles for output latency.
Create a Clear input? CLEAR_TYPE

NONE

ACLR

SCLR

NONE Select this option to create aclr or sclr signal for the complex multiplier.
Create a Clock Enable input? GUI_USE_CLKEN Unchecked Select this option to create ena signal for the complex multiplier clock.

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