Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Public
Document Table of Contents

4.1. Features

The LPM_MULT IP core offers the following features:

  • Generates a multiplier that multiplies two input data values
  • Supports data width of 1–256 bits
  • Supports signed and unsigned data representation format
  • Supports area or speed optimization
  • Supports pipelining with configurable output latency
  • Provides an option for implementation in dedicated digital signal processing (DSP) block circuitry or logic elements (LEs)
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the cascading of the DSP blocks.
  • Supports optional asynchronous clear and clock enable input ports
  • Supports optional synchronous clear for Intel® Stratix® 10, Intel® Arria® 10 and Intel® Cyclone® 10 GX devices

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