Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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6.5. Ports

The following tables list the input and output ports for the LMP_COMPARE IP core.

Table 18.  LPM_COMPARE IP core Input Ports
Port Name Required Description
dataa[] Yes Data input. The size of the input port depends on the LPM_WIDTH parameter value.
datab[] Yes Data input. The size of the input port depends on the LPM_WIDTH parameter value.
clock No Clock input for pipelined usage. The clock port provides the clock input for a pipelined operation. For LPM_PIPELINE values other than 0 (default), the clock port must be enabled.
clken No Clock enable for pipelined usage. When the clken port is asserted high, the comparison operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear for pipelined usage. The pipeline initializes to an undefined (X) logic level. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal.
Table 19.  LPM_COMPARE IP core Output Ports
Port Name Required Description
alb No Output port for the comparator. Asserted if input A is less than input B.
aeb No Output port for the comparator. Asserted if input A is equal to input B.
agb No Output port for the comparator. Asserted if input A is greater than input B.
ageb No Output port for the comparator. Asserted if input A is greater than or equal to input B.
aneb No Output port for the comparator. Asserted if input A is not equal to input B.
aleb No Output port for the comparator. Asserted if input A is less than or equal to input B.

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