Intel FPGA Integer Arithmetic IP Cores User Guide

ID 683490
Date 10/05/2020
Document Table of Contents

14.6. Parameters

The following table lists the parameters for the PARALLEL_ADD IP core.
Table 60.  PARALLEL_ADD Parameters
Parameter Name Type Required Description
WIDTH Integer Yes Specifies the width of the data[] input port.
SIZE Integer Yes Specifies the number of inputs to add.
WIDTHR Integer Yes Specifies the width of the result[] output port.
SHIFT Integer Yes Specifies the relative shift of the data vectors.
NEW_SUBTRACT String No Specifies whether to add or subtract the most significant input word bit. Values are NO or YES. If omitted, the default value is NO.
REPRESENTATION String No Specifies whether the input is signed or unsigned. Values are UNSIGNED or SIGNED. If omitted, the default value is UNSIGNED.
PIPELINE Integer No Specifies the value, in clock cycles, of the output latency.
RESULT_ALIGNMENT String No Specifies the alignment of the result port. Values are MSB or LSB. If omitted, the default value is LSB.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. The parameter editor calculates this value.
LPM_HINT String No

When you instantiate a library of parameterized modules (LPM) function in a VHDL Design File (.vhd), you must use the LPM_HINT parameter to specify an Intel® -specific parameter. For example: LPM_HINT = "CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YES"

The default value is UNUSED.
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL design files.

Did you find the information on this page useful?

Characters remaining:

Feedback Message