Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
Public
Document Table of Contents

8.1. Features

The Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP core offers the following features:

  • Generates a multiplier to perform multiplication operations of two complex numbers
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the cascading of the DSP blocks.
  • Supports data widths of 1– 256 bits
  • Supports signed and unsigned data representation format
  • Supports pipelining with configurable input latency
  • Provides an option to dynamically switch between signed and unsigned data support
  • Provides an option to dynamically switch between add and subtract operation
  • Supports optional asynchronous and synchronous clear and clock enable input ports
  • Supports systolic delay register mode
  • Supports pre-adder with 8 pre-load coefficients per multiplier
  • Supports pre-load constant to complement accumulator feedback

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