E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 8/30/2022
Public

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2.9.9. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example

There are two new Dynamic Reconfiguration transitions:
  • 100G NRZ with RSFEC [KR-FEC (528,514)] / without RSFEC <--> 100G NRZ with RSFEC [KP-FEC (544,514)]
  • 100G NRZ with RSFEC [KR-FEC (528,514)] / without RSFEC <--> 100G PAM4 with RSFEC [KP-FEC (544,514)]
The following figure provides an overview of the Dynamic Reconfiguration transitions.
Figure 32. Dynamic Reconfiguration Transitions
To achieve the dynamic reconfiguration modes listed above, the 100G Dynamic Reconfiguration Design Example has been enhanced and the required modifications are described below:
  1. 100G Ethernet IP:
    • The parameter DR_100G_NRZ_PAM4 needs to be set in the IP.
    • This is because the power up mode for the 100G Ethernet IP is in 100G NRZ mode. In this power up mode, the parallel clock is running at 402.8 MHz. When the Ethernet IP is configured to 100G PAM4 mode after performing dynamic reconfiguration, the parallel clock runs at a higher frequency which is 415 MHz.
    • Therefore, to ensure Intel® Quartus® Prime Timing Analyzer covers and analyzes the timing performance when the design is running at either NRZ mode or PAM4 mode, two timing profiles need to be available for the proper analysis to be performed. When this parameter is set, you observe two timing profile clocks reported in Timing Analyzer, whereby:
      • timing profile 0 is for power-up mode (100G NRZ) - 402.8MHz
      • timing profile 1 for 100G PAM4 mode – 415MHz
  2. C-code files – dynamic_reconfig.cpp and dynamic_reconfig.h—C-codes to enable PAM4 and NRZ [KP-FEC (544,514)] Dynamic Reconfiguration transition support.
  3. Hex file—Hex file generated for design simulation and hardware run.

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