Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

28.4.1. Selecting PLL Output Frequency and Phase

You select PLL output frequency and phase with controls in the PHY Settings tab. In the HPS, PLL frequencies and phases are set by software at system startup. A PLL might not be able to produce the exact frequency that you specify in Memory clock frequency. Normally, the Quartus Prime software sets Achieved memory clock frequency to the closest achievable frequency, using an algorithm that tries to balance frequency accuracy against clock jitter. This clock frequency is used for timing analysis by the Timing Analyzer.

It is possible to use a different software algorithm for configuring the PLLs. You can force the Achieved memory clock frequency box to take on the same value as Memory clock frequency, by turning on Use specified frequency instead of calculated frequency in the PHY Settings tab, under Clocks.

Note: If you turn on Use specified frequency instead of calculated frequency, the Quartus Prime software assumes that the value in the Achieved memory clock frequency box is correct. If it is not, timing analysis results are incorrect.