Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

19.4.3. Clocks

Table 193.  USB OTG Controller Clock Inputs

All clocks must be operational when reset is released. No special handling is required on the clocks.

Clock Signal

Frequency

Functional Usage

usb_mp_clk

60 – 200 MHz

Drives the master and slave interfaces, DMA controller, and internal FIFO buffers

usb0_ulpi_clk

60 MHz

ULPI reference clock for usb0 from external ULPI PHY I/O pin

usb1_ulpi_clk

60 MHz

ULPI reference clock for usb1 from external ULPI PHY I/O pin