Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

17.4. DMA Controller Address Map and Register Definitions

The following DMAC register map spans a 4 KB region, consists of the following sections.

Figure 70. DMAC Summary Register Map
  • Control registers— allow you to control the DMAC.
  • DMA channel thread status registers—provide the status of the DMA channel threads.
  • AXI and loop counter status registers—provide the AXI transfer status and the loop counter status for each DMA channel thread.
  • Debug registers—enable the following functionality:
    • Allow you to send instructions to a thread when debugging the program code.
    • Allow system firmware to send instructions to the DMA manager thread.
  • Configuration registers—enable system firmware to identify the configuration of the DMAC and control the behavior of the watchdog.
  • Component ID registers— enable system firmware to identify peripherals. Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in an unpredictable behavior.