Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

20.3.2. FPGA Routing

Table 200.  SPI Master Signals for FPGA routing:
Signal Name Signal Width Direction Description
spim_txd 1 Out

Transmit data line for the SPI master

spim_rxd 1 In

Receive data line for the SPI master

spim_ss_in_n 1 In

Master Contention Input

spim_ssi_oe_n 1 Out

Output enable for the SPI master

spim_ss_0_n 1 Out

Slave Select 0

Slave select signal from SPI master

spim_ss_1_n 1 Out

Slave Select 1

Allows second slave to be connected to this master

spim_ss_2_n 1 Out

Slave Select 2

Allows third slave to be connected to this master

spim_ss_3_n 1 Out

Slave Select 3

Allows fourth slave to be connected to this master

Table 201.  SPI Slave Signals for FPGA Routing
spis_txd 1 Out

Transmit data line for the SPI slave

spis_rxd 1 In

Receive data line for the SPI slave

spis_ss_in_n 1 In

Master Contention Input

spis_ssi_oe_n 1 Out

Output enable for the SPI slave

spis_sclk_in 1 In

Serial clock input