Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

9.3.2. Functional Description of the FPGA-to-HPS Bridge

The FPGA-to-HPS bridge provides access to the peripherals and memory in the HPS. This access is available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is exposed to the FPGA fabric, to support 32-, 64-, or 128-bit data. The master interface of the bridge, connected to the L3 interconnect, has a data width of 64 bits.

Table 40.  FPGA-to-HPS Bridge PropertiesThe following table lists the properties of the FPGA-to-HPS bridge, including the configurable slave interface exposed to the FPGA fabric.
Bridge Property FPGA Slave Interface L3 Master Interface

Data width19

32, 64, or 128 bits

64 bits

Clock domain

f2h_axi_clk l3_main_clk

Byte address width

32 bits

32 bits

ID width

8 bits

8 bits

Read acceptance

16 transactions

16 transactions

Write acceptance

16 transactions

16 transactions

Total acceptance

32 transactions

32 transactions

The FPGA-to-HPS bridge address map contains a GPV. The GPV registers provide settings that adjust the bridge slave properties when the FPGA slave interface is configured to be 32 or 128 bits wide. The slave issuing capability can be adjusted, through the fn_mod register, to allow one or multiple transactions to be outstanding in the HPS. The slave bypass merge feature can also be enabled, through the bypass_merge bit in the fn_mod2 register. This feature ensures that the upsizing and downsizing logic does not alter any transactions when the FPGA slave interface is configured to be 32 or 128 bits wide.

Note: It is critical to provide the correct l4_mp_clk clock to support access to the GPV, as described in "GPV Clocks".
19 The bridge slave data width is user-configurable at the time you instantiate the HPS component in your system.