Cyclone® V Hard Processor System Technical Reference Manual
ID
683126
Date
12/03/2024
Public
1. Cyclone® V Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. Scan Manager
8. System Interconnect
9. HPS-FPGA Bridges
10. Cortex®-A9 Microprocessor Unit Subsystem
11. CoreSight* Debug and Trace
12. SDRAM Controller Subsystem
13. On-Chip Memory
14. NAND Flash Controller
15. SD/MMC Controller
16. Quad SPI Flash Controller
17. DMA Controller
18. Ethernet Media Access Controller
19. USB 2.0 OTG Controller
20. SPI Controller
21. I2C Controller
22. UART Controller
23. General-Purpose I/O Interface
24. Timer
25. Watchdog Timer
26. CAN Controller
27. Introduction to the HPS Component
28. Instantiating the HPS Component
29. HPS Component Interfaces
30. Simulating the HPS Component
31. Register Address Map for Cyclone V HPS
A. Booting and Configuration
8.3.1. Master to Slave Connectivity Matrix
8.3.2. System Interconnect Address Spaces
8.3.3. Master Caching and Buffering Overrides
8.3.4. Security
8.3.5. Configuring the Quality of Service Logic
8.3.6. Cyclic Dependency Avoidance Schemes
8.3.7. System Interconnect Master Properties
8.3.8. Interconnect Slave Properties
8.3.9. Upsizing Data Width Function
8.3.10. Downsizing Data Width Function
8.3.11. Lock Support
8.3.12. FIFO Buffers and Clock Crossing
8.3.13. System Interconnect Resets
10.3.1. Functional Description
10.3.2. Implementation Details
10.3.3. Cortex®-A9 Processor
10.3.4. Interactive Debugging Features
10.3.5. L1 Caches
10.3.6. Preload Engine
10.3.7. Floating Point Unit
10.3.8. NEON* Multimedia Processing Engine
10.3.9. Memory Management Unit
10.3.10. Performance Monitoring Unit
10.3.11. Arm* Cortex* -A9 MPCore Timers
10.3.12. Generic Interrupt Controller
10.3.13. Global Timer
10.3.14. Snoop Control Unit
10.3.15. Accelerator Coherency Port
11.1. Features of CoreSight* Debug and Trace
11.2. Arm* CoreSight* Documentation
11.3. CoreSight Debug and Trace Block Diagram and System Integration
11.4. Functional Description of CoreSight Debug and Trace
11.5. CoreSight* Debug and Trace Programming Model
11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.4.1. Debug Access Port
11.4.2. System Trace Macrocell
11.4.3. Trace Funnel
11.4.4. CoreSight Trace Memory Controller
11.4.5. AMBA* Trace Bus Replicator
11.4.6. Trace Port Interface Unit
11.4.7. Embedded Cross Trigger System
11.4.8. Program Trace Macrocell
11.4.9. HPS Debug APB* Interface
11.4.10. FPGA Interface
11.4.11. Debug Clocks
11.4.12. Debug Resets
12.1. Features of the SDRAM Controller Subsystem
12.2. SDRAM Controller Subsystem Block Diagram
12.3. SDRAM Controller Memory Options
12.4. SDRAM Controller Subsystem Interfaces
12.5. Memory Controller Architecture
12.6. Functional Description of the SDRAM Controller Subsystem
12.7. SDRAM Power Management
12.8. DDR PHY
12.9. Clocks
12.10. Resets
12.11. Port Mappings
12.12. Initialization
12.13. SDRAM Controller Subsystem Programming Model
12.14. Debugging HPS SDRAM in the Preloader
12.15. SDRAM Controller Address Map and Register Definitions
14.1. NAND Flash Controller Features
14.2. NAND Flash Controller Block Diagram and System Integration
14.3. NAND Flash Controller Signal Descriptions
14.4. Functional Description of the NAND Flash Controller
14.5. NAND Flash Controller Programming Model
14.6. NAND Flash Controller Address Map and Register Definitions
15.1. Features of the SD/MMC Controller
15.2. SD/MMC Controller Block Diagram and System Integration
15.3. SD/MMC Controller Signal Description
15.4. Functional Description of the SD/MMC Controller
15.5. SD/MMC Controller Programming Model
15.6. SD/MMC Controller Address Map and Register Definitions
16.1. Features of the Quad SPI Flash Controller
16.2. Quad SPI Flash Controller Block Diagram and System Integration
16.3. Interface Signals
16.4. Functional Description of the Quad SPI Flash Controller
16.5. Quad SPI Flash Controller Programming Model
16.6. Quad SPI Flash Controller Address Map and Register Definitions
16.4.1. Overview
16.4.2. Data Slave Interface
16.4.3. SPI Legacy Mode
16.4.4. Register Slave Interface
16.4.5. Local Memory Buffer
16.4.6. DMA Peripheral Request Controller
16.4.7. Arbitration between Direct/Indirect Access Controller and STIG
16.4.8. Configuring the Flash Device
16.4.9. XIP Mode
16.4.10. Write Protection
16.4.11. Data Slave Sequential Access Detection
16.4.12. Clocks
16.4.13. Resets
16.4.14. Interrupts
18.6.1. System Level EMAC Configuration Registers
18.6.2. EMAC FPGA Interface Initialization
18.6.3. EMAC HPS Interface Initialization
18.6.4. DMA Initialization
18.6.5. EMAC Initialization and Configuration
18.6.6. Performing Normal Receive and Transmit Operation
18.6.7. Stopping and Starting Transmission
18.6.8. Programming Guidelines for Energy Efficient Ethernet
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
19.1. Features of the USB OTG Controller
19.2. USB OTG Controller Block Diagram and System Integration
19.3. USB 2.0 ULPI PHY Signal Description
19.4. Functional Description of the USB OTG Controller
19.5. USB OTG Controller Programming Model
19.6. USB 2.0 OTG Controller Address Map and Register Definitions
26.3.1.1.1. Message Valid (MsgVal)
26.3.1.1.2. New Data (NewDat)
26.3.1.1.3. Message Lost (MsgLst)
26.3.1.1.4. Interrupt Pending (IntPnd)
26.3.1.1.5. Transmit Interrupt Enable (TxIE)
26.3.1.1.6. Receive Interrupt Enable (RxIE)
26.3.1.1.7. Remote Enable (RmtEn)
26.3.1.1.8. Transmit Request (TxRqst)
26.3.1.1.9. End of Block (EoB)
30.1. Simulation Flows
30.2. Clock and Reset Interfaces
30.3. FPGA-to-HPS AXI Slave Interface
30.4. HPS-to-FPGA AXI Master Interface
30.5. Lightweight HPS-to-FPGA AXI Master Interface
30.6. FPGA-to-HPS SDRAM Interface
30.7. HPS-to-FPGA MPU Event Interface
30.8. Interrupts Interface
30.9. HPS-to-FPGA Debug APB* Interface
30.10. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
30.11. HPS-to-FPGA Cross-Trigger Interface
30.12. HPS-to-FPGA Trace Port Interface
30.13. FPGA-to-HPS DMA Handshake Interface
30.14. Boot from FPGA Interface
30.15. General Purpose Input Interface
A.7.2. Partial Reconfiguration
Partial reconfiguration allows you to reconfigure part of the device while other sections remain running. The HPS performs partial reconfiguration while the FPGA portion of the device is in user mode. The following sequence suggests one way for software to perform a partial configuration:
- If PR_READY=1, continue to step 7.
- If PR_READY is 0, then go back and repeat step 5. Note that a minimum of 16 DCLK pulses are required.
If the HPS resets in the middle of a partial reconfiguration, software can assume that the configuration is unsuccessful. After an HPS warm reset, software must repeat the steps for partial configuration. After an HPS cold reset, software must repeat the steps for Full Configuration.
- Read the mode bit of the stat register in fpgamgrregs to ensure that the FPGA is in user mode.
- Set the cdratio bit of the ctrl register to match the characteristics of the partial reconfiguration image and set the cfgwdth bit of the ctrl register to 0 for 16-bit configuration data width.
- Set the en bit of the ctrl register to 1 to give the FPGA manager control of the configuration input signals.
- Set the prreq bit of the ctrl register to 1 to assert PR_REQUEST.
- Write a value of 1 to the dclkcnt register to generate DCLK pulses for one clock cycle.
- Poll the fpgamgrregs.mon registers to observe the PR_READY (prr) bit.
- Write a value of 3 to the dclkcnt register to generate DCLK pulses for three clock cycles.
- Set the axicfgen bit of the ctrl register to 1 to enable sending configuration data to the FPGA.
- Write the partial reconfiguration image to the data register in the FPGA manager fpgamgrdata registers. You can also choose to use a DMA to transfer the configuration image from a peripheral device to the FPGA manager.
- Poll the fpgamgrregs.mon registers to observe the PR_DONE (prd), PR_READY (prr), PR_ERROR (pre), and CRC_ERROR (crc) bits until the bits match one of the completion statuses shown in Table A–12.
- Set the axicfgen bit of the ctrl register to 0 to disable sending configuration data to the FPGA.
- Set the prreq bit of the ctrl register to 0 to deassert PR_REQUEST.
- Write a value of 128 to the dclkcnt register to generate DCLK pulses for 128 clock cycles.
- Poll the dcntdone bit of the dclkstat register until it changes to 1, which indicates that all the DCLKs have been sent.
- Write a 1 to the dcntdone bit of the dclkstat register to clear the completed status flag.
- Poll the fpgamgrregs.mon registers to observe the PR_DONE (prd), PR_READY (prr), PR_ERROR (pre), and CRC_ERROR (crc) bits. When all bits are set to 0, the FPGA is ready for the next transaction.
- Set the en bit of the ctrl register to 0 to allow the external pins to drive the configuration input signals.