Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

20.3.1. Interface to HPS I/O

Table 198.  SPI Master Interface Pins
Signal Name Signal Width Direction Description
CLK 1 Out

Serial clock output from the SPI master

MOSI 1 Out

Transmit data line for the SPI master

MISO 1 In

Receive data line for the SPI master

SS0 1 Out

Slave Select 0

Slave select signal from SPI master

SS1 1 Out

Slave Select 1

Slave select signal from SPI master

Table 199.  SPI Slave Interface Pins
CLK 1 In

Serial clock input to the SPI slave

MOSI 1 In

Receive data line for the SPI slave

MISO 1 Out

Transmit data line for the SPI slave

SS0 1 In

Slave select input to the SPI slave