Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

30.6. FPGA-to-HPS SDRAM Interface

The HPS component contains a memory interface simulation model to which all of the FPGA‑to‑HPS SDRAM interfaces are connected. The model is based on the HPS implementation and provides cycle‑level accuracy, reflecting the true bandwidth and latency of the interface. However, the model does not have the detailed configuration provided by the HPS software, and hence does not reflect any inter‑port scheduling that might occur under contention on the real hardware when different priorities or weights are used.