Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

20.5.3. Slave SPI and SSP Serial Transfers

Figure 102. Slave SPI or SSP Serial Transfer Software Flow

To complete a continuous serial transfer from a serial master to the SPI slave, follow these steps:

  1. If the SPI slave is enabled, disable it by writing 0 to SSIENR.
  2. Set up the SPI control registers for the transfer. You can set these registers in any order.
    • Write CTRLR0 (for SPI transfers, set SCPH and SCPOL identical to the master device).
    • Write TXFTLR and RXFTLR to set FIFO buffer threshold levels.
    • Write the IMR register to set up interrupt masks.
  3. Enable the SPI slave by writing 1 to the SSIENR register.
  4. If the transfer mode is transmit and receive (TMOD= 0) or transmit only (TMOD= 1), write data for transmission to the master into the transmit FIFO buffer (write DR). If the transfer mode is receive only (TMOD= 2), you need not write data into the transmit FIFO buffer. The current value in the transmit shift register is retransmitted.
  5. The SPI slave is now ready for the serial transfer. The transfer begins when a serial‑master device selects the SPI slave.
  6. When the transfer is underway, the BUSY status can be polled to return the transfer status. If a transmit FIFO empty interrupt request is made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read the receive FIFO buffer (read DR).
  7. The transfer ends when the serial master removes the select input to the SPI slave. When the transfer is completed, the BUSY status is reset to 0.
  8. If the transfer mode is not transmit only (TMOD != 1), read the receive FIFO buffer until empty.
  9. Disable the SPI slave by writing 0 to SSIENR.