Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

10.5.1.1. Cache Controller Configuration

The L2 cache consists of the Arm* L2C‑310 L2 cache controller configured as follows:

  • 512 KB total memory
  • Eight‑way associativity
  • Physically addressed, physically tagged
  • Line length of 32 bytes
  • Critical first word linefills
  • Support for all AXI cache modes
    • Write‑through
    • Write‑back
    • Read allocate
    • Write allocate
    • Read and write allocate
  • Single event upset (SEU) protection
    • Parity on Tag RAM
    • ECC on L2 Data RAM
  • Two slave ports mastered by the SCU
  • Two master ports connected to the following slave ports:
    • SDRAM controller, 64-bit slave port width
    • L3 interconnect, 64-bit slave port width
  • Cache lockdown capabilities as follows:
    • Line lockdown
    • Lockdown by way
    • Lockdown by master (both processors and ACP masters)
  • TrustZone* support
  • Cache event monitoring