Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 12/03/2024
Public

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Document Table of Contents

19.5.1. Enabling ECC

  1. Turn on the ECC hardware, but disable the interrupts.
  2. Initialize the SRAM in the peripheral.60
  3. Clear the ECC event bits, because these bits may have become asserted after Step 1.
  4. Enable the ECC interrupts now that the ECC bits have been set.
60 This is the case for the following peripherals: SD/MMC, NAND, On-Chip, DMA, USB, and EMAC.