Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

14.4.9.1. Multi-Transaction DMA Command

The NAND flash controller processes multitransaction DMA commands only if it receives all four command‑data pairs in order. The flash controller responds to out‑of‑order commands with an unsup_cmd interrupt. The flash controller also responds with an unsup_cmd interrupt if sequenced commands are interleaved with other flash controller MAP commands.

To initiate DMA with a multitransaction DMA command, you send four command‑data pairs to the NAND flash controller through the Control and Data registers in the nanddata region, as shown in "Command-Data Pair Formats".