Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

16.5.5. Indirect Write Operation with DMA Enabled

The following steps describe the general software flow to set up the quad SPI controller for indirect write operation with the DMA enabled:

  1. Perform the steps described in the Setting Up the Quad SPI Flash Controller section.
  2. Set the flash memory start address in the indwrstaddr register.
  3. Set the number of bytes to be transferred in the indcnt field of the indwr register.
  4. Set the indirect transfer trigger address in the indaddrtrig register.
  5. Set the number of bytes for single and burst type DMA transfers in the dmaper register.
  6. Optionally set the SRAM watermark level in the indwrwater register to control the rate DMA requests are issued. The value set must be greater than one flash page. For more information, refer to the Indirect Write Operation section.
  7. Start the indirect write access by setting the start field of the indirwr register to 1.
  8. Either use the indirect complete interrupt to determine when the indirect write operation has completed or poll the completion status of the indirect write operation through the ind_ops_done_status field of the indwr register.