Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

3.3.3.3.1. Flash Controller Clocks

Flash memory peripherals can be driven by the main PLL, the peripheral PLL, or from clocks provided by the FPGA fabric.

Figure 8. Flash Peripheral Clock Divide and Gating
Table 13.  Flash Controller Clocks

System Clock Name

Frequency

Divided From

Constraints and Notes

qspi_clk

Up to 432 MHz

Peripheral PLL C2, main PLL C3, or f2h_periph_ref_clk

Clock for quad SPI, typically 108 and 80 MHz

nand_x_clk

Up to 250 MHz

Peripheral PLL C3, main PLL C4, or f2h_periph_ref_clk

NAND flash controller master and slave clock

nand_clk

nand_x_clk/4

Peripheral PLL C3, main PLL C4, or f2h_periph_ref_clk

Main clock for NAND flash controller, sets base frequency for NAND transactions

sdmmc_clk

Up to 200 MHz

Peripheral PLL C3, main PLL C4, or f2h_periph_ref_clk

  • Less than or equal to memory maximum operating frequency
  • 45% to 55% duty cycle
  • Typical frequencies are 25 and 50 MHz
  • SD/MMC has a subclock tree divided down from this clock